In recent years, along with the advancement of the digital techniques in electronic devices, demands for nonvolatile memory devices have been increasing for storage of data, such as a picture, and the like. Further, demands for increasing the capacity of a memory device, reducing the write power, shortening the read and write times, and prolonging the device's life have been escalating. To meet such demands, U.S. Pat. No. 6,204,139 (Patent Document 1) discloses a technique for forming a nonvolatile memory device using a perovskite material whose resistance value varies according to an applied electric pulse (e.g., Pr(1-X)CaXMnO3 (PCMO), LaSrMnO3 (LSMO), GdBaCoXOY (GBCO), etc.). According to the technique disclosed in this publication, a predetermined electric pulse is applied to these materials (hereinafter, generically referred to as “variable-resistance material(s)”) to increase or decrease the resistance value of the materials. The resistance value which has varied as a result of application of the pulse is used for memorization of different values. Based on this scheme, the materials are used for memory devices.
U.S. Pat. No. 6,673,691 (Patent Document 2) discloses a method for changing the resistance value of a variable-resistance material by changing the pulse width of an electric pulse. U.S. Pat. No. 6,673,691 further discloses an example of a 1D1R (1 diode/1 resistor) memory cell array wherein a memory cell is formed using these variable-resistance materials, and a diode is used as a memory cell selection device. An advantage of this structure is a smaller memory cell size as compared with a structure which includes a transistor as a memory cell selection device.
FIG. 21 shows a memory device (1D1R nonvolatile memory device) 900 formed using a conventional variable-resistance material disclosed in U.S. Pat. No. 6,673,691. In this conventional example, the memory device 900 includes a substrate 901, a P/N junction diode (N-type Si region 902, P-type Si regions 903-1 and 903-2) formed on the substrate 901, a lower electrode 904-1 formed on the P-type Si region 903-1 of the diode, a lower electrode 904-2 formed on the P-type Si region 903-2 of the diode, a contact plug 905 formed on the N-type Si region 902 of the diode, a variable-resistance material layer 906 formed over the lower electrodes 904-1 and 904-2, and upper electrodes 907-1 and 907-2 formed on the variable-resistance material layer 906. In this conventional example, the lower electrodes 904-1 and 904-2 and the upper electrodes 907-1 and 907-2 are formed of Pt, and the variable-resistance material layer 906 is formed of P0.7Ca0.3MnO3.
In the memory device 900 shown in FIG. 21, when a predetermined pulse is applied between the upper electrode 907-1 and the lower electrode 904-1, the resistance value of a portion of the variable-resistance material layer 906 between the upper electrode 907-1 and the lower electrode 904-1 (variable region 906α) is varied. When a predetermined pulse is applied between the upper electrode 907-2 and the lower electrode 904-2, the resistance value of a portion of the variable-resistance material layer 906 between the upper electrode 907-2 and the lower electrode 904-2 (variable region 906β) is varied. That is, in this memory device, each of the variable region 906α and the variable region 906β is used as a single memory cell.
In the memory device 900 shown in FIG. 21, the P/N junction diode formed on the substrate 901 is used as a diode for selection of memory cells. Thus, an electric current flows from the upper electrode 907-1 (907-2) to the lower electrode 904-1 (904-2) (forward direction) but does not flow from the lower electrode 904-1 (904-2) to the upper electrode 907-1 (907-2) (reverse direction) or between the upper electrode 907-1 and the upper electrode 907-2.
FIG. 22 shows an equivalent circuit of the memory device 900 of FIG. 21. In FIG. 22, a word line W1 corresponds to the upper electrode 907-1, a word line W2 corresponds to the upper electrode 907-2, and a bit line B1 corresponds to the contact plug 905. A memory cell MC911 corresponds to the variable region 906α, a diode D911 corresponds to the diode (N-type Si region 902, P-type Si region 903-1), a memory cell MC912 corresponds to the variable region 906β, and a diode D912 corresponds to the diode (N-type Si region 902, P-type Si region 903-2).
<Operation>
Next, an operation of the memory device 900 of FIG. 21 is described with reference to FIG. 22. Herein, a process with the memory cell MC911 is described.
[Set (Memorization) or Reset]
In a memorization process, the word line W2 and the bit line B1 are pulled down to the ground, and a predetermined electric pulse is applied to the word line W1. As a result, the resistance value of the memory cell MC911 changes to a low resistance state (reset) or high resistance state (set). In an example disclosed in U.S. Pat. No. 6,673,691, when a pulse voltage having a voltage value of +4 V and a pulse width of 100 nsec is applied, the resistance value of the memory cell MC911 changes from the high resistance state to the low resistance state. When a pulse voltage having a voltage value of +2.5 V and a pulse width of 10 μsec is applied, the resistance value of the memory cell MC911 changes from the low resistance state to the high resistance state.
[Reproduction]
In a reproduction process, the word line W2 and the bit line B1 are pulled down to the ground, and a predetermined reproduction voltage (e.g., a voltage having a voltage value of +0.5 V) is applied to the word line W1. As a result, the electric current flowing through the memory cell MC911 is released to the bit line B1. On the other hand, no electric current flows through the memory cell MC912. Since the diode D912 (the N-type Si region 902 and P-type Si region 903-2 of FIG. 21) is provided to the memory cell MC912, no electric current flows from the word line W1 to the word line W2. Thus, only the resistance value of the memory cell MC911 can be detected.
According to the schemes as described above, the conventional memory device (1D1R nonvolatile memory device) 900 performs recording or reproduction in each memory cell.
U.S. Pat. No. 6,531,371 (Patent Document 3) realizes a larger-capacity memory device by constructing a cross point type memory device using a variable-resistance material. Specifically, as shown in FIG. 23, the intersections (cross points) of word lines W1 and W2 and bit lines B1 and B2 are respectively provided with memory cells 90-11, 90-12, 90-21, and 90-22, whereby the cross point type memory device is realized. The memory cells 90-11 through 90-22 are formed of a variable-resistance material.
However, in the memory device of FIG. 23, if a memory cell adjacent to a target memory cell from which information is to be read (e.g., variable-resistance material portions 90-11, 90-12, 90-22 adjacent to variable-resistance material portion 90-21) has a low resistance value, a current flows not only through the target memory cell but also through the adjacent memory cell as shown in FIG. 23, so that there is a possibility that the state of resistance in the target memory cell cannot be determined. In view of such, as disclosed in Japanese PCT National Phase Laid-Open Patent Publication No. 2002-530850 (Patent Document 4), a cross point type memory device has been proposed wherein a state-variable portion functioning as a memory cell and a diode called a steering portion are connected in series.
[Patent Document 1] U.S. Pat. No. 6,204,139
[Patent Document 2] U.S. Pat. No. 6,673,691
[Patent Document 3] U.S. Pat. No. 6,531,371
[Patent Document 4] Japanese PCT National Phase Laid-Open Patent Publication No. 2002-530850
[Non-Patent Document 1] 2002 IEDM, Article No. 7.5, December 2002